1. Priority Claim
This application claims the benefit of priority from U.S. Provisional Patent Application No. 60/830,166 filed 11 Jul. 2006.
2. Technical Field
This disclosure relates to a digital signal processing architecture. In particular, this disclosure relates to a pipelined digital signal processing architecture.
3. Related Art
The relentless pursuit of speed and throughput has driven microprocessor architectures through many significant increases in complexity and has yielded many significant architectural enhancements. A limitation to the speed of a microprocessor architecture is the settling time of the digital circuitry between register states. One enhancement to increase microprocessor architecture speed is the pipeline. The pipeline increases processor speed by subdividing major sections of circuitry into pipeline stages to reduce the digital circuit settling time (e.g., an instruction decode stage and an instruction execution stage) and allow the clock speed to increase.
But, by introducing pipeline stages into the architecture there also arise partially completed instructions that will not be finally resolved until they propagate through the entire pipeline. These partially completed instructions can have a negative impact on the processing efficiency by creating pipeline stalls (i.e. unused pipeline stages) for instructions that need a completed result of a previous instruction before being able to complete. A pipeline stall is one or more unused execution cycles within the pipeline that delays the execution of a program instruction until the result of a prior instruction is ready for the currently executing program instruction.
In an effort to avoid pipeline stalls, immense amounts of time, cost, and other resources were consumed to arrive at coding techniques and compilers that were able to optimize a program to run with fewer stalls. For example, some compilers attempted to reorganize program instructions to eliminate interdependencies between instructions that lead to stalls. However, reorganizing the program was not possible in every instance. Furthermore, even if the program or a portion of the program could be reorganized, the resulting scrambled code was invariably difficult to read, understand, and maintain.
There is a need for an improved pipelined processing architecture.